Universal logic block



Sept. 13, 1960 E. F. YHAP UNIVERSAL LQGIC BLOCK 4 Sheets-Sheet 1 Filed Sept. 11, 1959 M o/ R H m m C m m M 0W M N m Q o o N Y a T j J n/ mi. 2/ J Q K3 :a1 m 1 2: 1...! 232:5 :wzf: 2) All 1 L f .E E 1F E. N\ ld w 2 l i1- n @E #HHH .ishmwil Sept. 13, 1960 E. F. YHAP UNIVERSAL LOGIC BLOCK 4 Sheets-Sheet 2 Filed Sept. ll, 1959 om INE TNQ @NEU -NH T JWJ IJ QL of L| om TNQ Irl Sept. 13, 1960 E. F. YHAP UNIVERSAL LOGIC BLOCK 4 Sheets-Sheet 3 Filed Sept. 11, 1959 Ill sept. 13, 1960 E. F. YHAP 2,952,792

UNIVERSAL LOGIC BLOCK Filed Sept. l1, 1959 4 Sheets-Sheet 4 SAMPLE 16M C Q OUTPUT CrfhI CF 16I\\`1 FIG. 6

United States Patent O UNIVERSAL LOGIC BLOCK Ernesto F. Yhap, Poughkeepsie, N.Y., assiguor to International Business Machines Corporation, New York, N.Y., a corporation of New York Filed Sept. 11, 1959, Ser. No. 839,401

6 Claims. (Cl. 313-108) This invention relates to an electronic switching device, and more particularly to a device which may be interconnected with a multiplicity of like devices to form -a complete switching system. The device, which forms a basic computer building block, may be termed a universal llogic block.

A universal logic block must be capable of producing, on demand, `an electrical representation of the presence of a desired one of a plurality of distinct conditions. For a three variable system there are 6 distinct inputs, X, Y, Z, not X, not Y, and not Z. The not function of any variable is generally shown by a horizontal bar over the letter or numeral designating the variable, for example, not X is X. A three variable system permits 8 different simple combinations, which may be assigned numbers according to their 4binary values, as follows:

XYZ: (Read: Not X and not Y and not Z is assigned numberO) XTX-2:4121 XYZ-:#2 YZ=#3 XYZ-:#4 XYZ=#5 XYZ=#6 XYZ=#7 In addition to the simple combinations, many complex combinations are available. Such combinations may be stated in algebraic form, using to denote the alternative (or) yfunction as follows:

There are many other complex combinations possible with ,three variables.

For systems of four, iive or more variables, binary values may be similarly Aassigned to each of the 1-6, 32 or more simple combinations, and complex combinations may similarly be set up.

Prior art universal logic blocks generally have been made up of plural OR circuits, AND circuits, and one or more powering devices such as tubes or transistors. lA1- -though effective electrically, such universal logic blocks have not become widely used because they cannot compete `in price with specially Ydesigned circuit elements. Redundancies of components, such asdiodes, and a `.necessity for lines to cross one another, cause `such prior Vart universal logic blocks to -be somewhat dicult yto assemble and to package, which in turn makes'them expensive. Printed circuit techniques become difficult because `of fthe multiplicity of active elements such as diodes and transistors, yand because of the crossovers of the interconnecting wires.

It is therefore an object of this invention to provide :a low-cost universal logic block which is .subject tomanufacture using printed circuit techniques.

It is another `object of 'this invention torprovide a 11mi- Y 2,952,792 Patented Sept. 13, 1960 ICS versal logic block in which there is no need for electrical conducting lines t0 cross over each other.

It is a further object of this invention to provide a universal logic block which is susceptible to use in systems having 2, 3, 4, or more variables.

It is la further object of the invention to provide a universal logic block which may be -set to any of the functions of which it is capable according to a simple conversion table.

It is another object of the invention to provide a universal logic block which may be assigned differing functions at different periods in the machine cycle.

Another object of the invention is to provide a universal logic block which may be laid out on -two sides of a printed circuit card.

The foregoing iand other objects, features and advantages cf the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.

In the drawings: Y

Fig. l lis ya cross ysection of a preferred opt0-electronic embodiment .of .the invention, expanded in thickness to show various layers and connections.

Fig. 2 is a conversion table fora three variable system.

Fig. 3 is a preferred layout of conductors and switching elements on the switch side of a printed circuit card,

viewed from above `in Fig. l .as indicated by arrows marked Fig 3.

Fig. 4 is a preferred layout of conductors and switch operators viewed from above in Fig. 1 ,as indicated by arrows marked Fig 4. Fig. 4 shows the operator side SUMMARY The universal logic block comprises, Vfor an n-Variable system, n-I-l groups of switching elements and sucient switch operators to operate the switching elements. One group of switching elements is function-related; all others are variable-related. Variable linputs condition the related lswitch operations to render their related switch-ing elements conductive; Ithese variable inputs may correspond to output from' Aother universal logic blocks in previous portions of a logical machine. Function inputs condition the related switch operators to render their related function switching elements conductive; the function inputs may `also be machine controlled.

An electrical vsample pulse is provided to a sample bus which connects to all n+1 groups of switching elements. An output bus also connects to all n-l-l groups of'switching elements. lf the groups are designated X, Y, Z, (n+1), -a X switching kelement and an X switching lelement switch in series between the sample and output busses forms the X group. In the next, or Y group, a switching element and a Y switching element in series vshunt the 'X switching element; another --Y series pair shunts the X switching element. In the Z group four Z-Z series pairs connect the sample bus to the output bus, each pair shunting one of the Y or switching elements in the `tier above; in turn, pairs Vof --Y switching elements shunt the X or X switching elements in lthe group above.

Infgfoupu-l-fl, ZU/lseries pairs connect the sample bus l-) 3 and output bus, each switching element shunting one of the n or n switching elements in the group above. In

a three-variable system, there are eight switching elements,V

which may be designated 7,6,`5Q`. .'0, and can be re= lated to the function of the universal logic block by a conversion table. Forexample, switch #1, which is the conversion factor for X2Z, completes a conductive path from sample bus to the output bus only if the related combination, 22Z, is present.

Fig. l-Cross-section Fig. 1 illustrates an expanded cross section of a preferred embodiment of the invention, utilizing the system of logic variously called opt0-electronics, photologic, or ELPC (electroluminescence-photoconductivity) logic, in which switching elementsV arephotoconductors (PCS) and switch operators are electroluminescent lamps (ELs) facing the related PCs. Y f

The opt0-electronic universal logic block is a plate of so-called conductive glass, which more particularly may be described as a glass plate 11 having a thin coating 12 of tin oxideV or other conductive material on one face. Any array of PCs 13 are emplaced upon the insulative surface 14 of plate 11. The PCs may be applied bysilk screen printing techniques and sintered by known methods. A network of conductors 15, interconnecting PCS 13 asvwill be more particularly explained in connection A' with Fig. 3, are printed over the PCs, A plurality of terminals 16 supply sample and output signal paths when the plate is plugged into a suitable socket 17, which in turn has plural terminals which are interconnected with other switching circuits in the logical machine.

An EL layer 18 o-f phosphor-loaded dielectric covers most of the conductive face 12 of plate 11. This layer may be sprayed or knife-coated upon the'pl'ate afterlated in each pair to Y and 2, in series, pair 13Y-1 and 132-2 shunting the PC 13X and the pair 13Y-2 and 132-2 shunting the PC 132. Tier Z has four complementary pairs of PCs 13Z-1 and 132-1; 13Z-2 and 132-2; 13Z-3 and 132-3; 13Z-4 and 132-4 functionally related in each pair to Zand 2, in series, each pair shunting one of the PCs in the Y tier. Therevis no conductive path possible through the three-tiered lattice with no PCs illuminated, since in any'one of the many paths from sample terminal 16A to output terminal 16C there is a pair of complementary PCs, which by the rules are not coincidentally illuminated.

Function switch tier, 13-7 through'13-0, with all switches open, does not complete a conductive path from sample terminal 16A to output terminal 16C. With the current path thus open between sample and output terminals (the desired function not being present) the sample voltage is impressed across resistance 25 and appears at complement terminal 16D. When a Ifunction switch is closed and the related function is present, a conductive path' is completed through the function switch to connect the sample input terminal to the output terminal.

SIMPLE FUNCTIONS Function #0 YZ" The universal logic -block may be permanently set to yfunction #0 Iby a conductive paste spread over PC 13-0, or temporarily set to function #0 by a light which illuminates PC 13-0. With the function set, the universal logic block is expected to provide an output if the 2 PCs, the 2 PCs, and the 2 PCs are concurrently illuminated during a sampling period, and to provide an alternate output .if there is a discrepancy in the 222 appearance.

With X22 properly set in the switch operators, all X, 2, and 2 switches are conductive. 'I'he sample pulse at input terminal 16A traverses input bus 26, progresses along tier conductor 152 through PC 132 to the long into socket 17, which inA turn has plural terminals 22 y which are interconnected with other switching circuits in the logical machine. Y

Upon a portion of the conductive face 12 of plate 11 which is not covered by EL layer 18, a terminal 23 is placed. This terminal may be connected through the socket to ground potential of the logical machine. When suitable electrical potential is applied across an area such as 24 of EL layer 18 which lies between an electrode 19 and grounded conductive layer 12, area 24 luminesces, illuminating the associated PC 13, which conditions the PC for conduction.

Fig. 2-Conversz'on table For `the three-variable system illustrated, there are four tiers of PCs in a lattice network. There are three variable-related tiers, one for each variable, and a function-related tier. Tier X has a complementary pair of PCs 13X and 13X functionally related to X and X, in series between sample terminal 16A and output termif n'al 16C. Tier Y has two complementary pairs of PCs center -bus 28, through PC 132-2 to medium-length right center bus 29, through function switch PC 13-0 to out' put bus 31 to output terminal 16C.

F unction #5 X 2Z With X22 properlyV set in the switch operators, the similarly marked switches are conductive. The sample pulse at inpu-t 'terminal 16A traverses input bus 26, progresses through PC 132-1 to the medium-length left center bus 32, through function switch PC 13-5 to short bus 33, through PC 13Z-2 to the long center bus 28, through PC 13X to output bus 31.

The universal logic yblock operates similarly for other simple functions, the related function switch completing a conductive path through the variable `switches when the setup of the variable switches matches that of the function switch.

Complex functions When it is desired to synthesize, within a universal logic block, a complex function such as (X24-12X )Z, which may bestated X exclusive or Y and Z, it is necessary to reduce or expand the statement of the function into simple functions, as follows, to choose the proper function switches.

(XY-|-Y)Z=XYZ+YZ=#5+#3 The function switches are made conductive by a permanentV or transitory switch operator as previously described. yIf the variable switches yshould be set to X2Z at sample time, the simil-arly marked switches are conductive. The sample pulse at terminal 16A passes through 132-1, medium-length bus 32,*switch PC 137-5, short Y Y 33, through PC 1 3Z-2 tolong center bus 28, -through 13Y-1 and 13u-1; 13Yzrand .132-2 functionally rc 76 PC'13X to output bus 31.

If the variable switches are set to XYZ, the sample pulse at terminal 16A passes along input bus 26, through 13X to long center bus 2S, through switch PC 13-3 .to short bus 34, through PC 13Z-3 to medium-length b 29, and through 13Y-2 to the output bus 31.

I-f the variable switches are Iset -to XYZ, the sample pulse yat the input bus will be blocked, since switches XYZ, and 7 are open. If the variable switches are set to Z, the sample pulse will be blocked near the output bus, since switches X, Y, Z, and l lare open. Altern-ate outputs are generated as will be more particularly described under subheading Alternate Outputs.

In the three-variable system, Ia two-variable function is a complex function. Since Z is irrelevant, the function may be stated With XY properly set in the switch operators, the similarly marked variable switches are conductive as are function switches #7 and #6. The sample pulse at the input bus passes through switches #7 yand #6, bypassing Z-l and Z-1 and short bus 35 regardless of their set-ting, onto medium-length bus 32, through 13Y-1 to center bus 28, and through y-13X to output bus 31.

F ig. 4-Swv`tch operators One side of each EL area, the conductive plate electrode 12 is connected through terminal 21Q to ground. To condition any EL switch operator 19, it is necessary only to apply a suitable potential to the related terminal 21A-ZIP and the associated cond-uctor 20. For example, potential applied to terminal 21C causes lboth Y operator ELs to luminesce, potential applied to terminal 21N causes #7 operator EL to luminesce. The EL switch operators are light-coupled through conductive layer 11 and glass 12 to lthe related switch PCs (see Fig. 1).

Figs. 3 and 4-A lternate output For true universal operations, it is desired to drive several universal logic blocks from the output of a preceding universal logic block. Each universal logic block, therefore, is provided with two outputs representing fulllment of its function (output) 'and non-fulfillment (alternate output).

An inverter 40 is therefore included in the universal logic block. EL electrode 19-40 (Fig. 4) is connected through terminal 21P Iand the plug connector to output bus 31 and output terminal 16C (Fig. 3); the inverter EL luminesces during each output, illuminating PC 13--40 which in turn connects alternate output 16D to ground via conductor 41, PC 13-40, conductor 42, yand grounded terminal 16E. Should the output bus 31 not be conditioned, the sample pulse is connected via conductor 4S, resistance 25, and conductor 46 to PC 13-40 as a 'terminal and tothe alternate output terminal 16D via conductor 41.

Should the output bus be conditioned, the inverter EL lumincsces, illuminating PC 13--40. Although the sample pulse is connected via input bus 26, conductor 45, resistance 25, conductor 46, through illuminated PC 13-40, and conductor 41 to alternate output terminal 16D, PC 13-40, being illuminated, grounds alternate output terminal 16D via conductors 41 and 42. The sample voltage is impressed across resistance 25 in parallel to the output path. The impedance of the resistance 25 is chosen higher than that of n-l-l illuminated PCs in series with the maximum load; the impedance of resistance 25 must however not be so high as to drop the potential at alternate output terminal 16D to a value too low to operate ELs.

Figs. -7-0ther components The invention is not limited to ELPC logic, since there switches.

are other suitable components, of which superconductors of the .thin lm .type are particularly applicable.

A current mode superconductor universal logic block may be printed on two sides of a glass plate 51 .in the manner illustrated in Fig. 5. The Switch operator 52 is a field-producing area; the switching element 53 is the superconductor. A return path 54 as well as a signal path 55 for each switch operator 52 must be incorporated.

To preserve the constant current condition under which superconductors operate most advantageously, the inverter of the photologic embodiments Vis omitted in favor of complementary duplication, with two complete blocks', (Fig. 7) a true block Jand an alternate block, each having n tiers of variable switching elements and function In one set the function switching elements are designated 7 0; in the other they are designated in opposite sense as 7 6.

The sample pulse at 16A, lif the variables are set up corresponding to the function setup of the true set, iinds a superconductive path to output terminal 16C. There is a resistive path between input and output terminals of the alternate set. Conversely, if there is discrepancy between the variables and the function setup, there is no superconductive path between sample input aud true output; there is, however, a superconductive path between sample input and alternate output. A convenient wiring arrangement is to apply the sample pulse to terminal 16A of the true block, and to connect terminal 16B of the true block to terminal 16A of the alternate block.

For example, where the YZ) function is desired, switch operator 2 sets up the true block; in the alternate block, all function switching elements except the 5, and are made conductive by the related switch operators. The XYZ setup of the variables completes a superconductive path in the true block via terminal 16A, X, center bus 28, Z, switching element 2, bus 29 and Y to output bus 31 and terminal 16C. The superconductive path through the alternate block is open at function switching elements Z, and X. Should the variable setting be XY Z, the true block would be open at function switching element 6, Z, X, the alternate block superconductive via terminal 16A, input bus 26, function switching elements 5, center bus 28 and variable switching element X to output bus 31 and terminal 16C.

While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.

What is claimed is:

l. A universal logic block to signal the occurrence of a selected one of 2n possible functions of n variables comprising, in combination: structural means; a sample terminal; an output terminal; and a network including n groups of paired complementary Variable switching elements, the groups being assigned to the respective variables and interconnected in pyramidal lattice fashion so that each variable switching element is shunted by paired complementary switching elements of the next variable, group n having 2n switching elements in series relationship with each other and in series-parallel relationship with the remaining switching elements in said network; and 2n function switching elements, each shunting one of the said 211 switching elements in group n, whereby the operation of a selected function switching element and the operation of variable switching elements assigned to the selected function completes a conductive electrical path between said sample terminal and said output terminal.

2. A universal logic block as described in claim 1, wherein said structural means is a plate, said network of 7 switching elements are arrayed on one side of said plate, and related switch operators are arrayed on the other sideof said plate, coupled through said plate to operate said switching elements.

" 3; A universal logic blockas described in claim 2 terminal, and means operable in response to an output signal through one or more of said function switching elements to inhibit alternateutput signals.

5. A universal logic block as described in claim 4, in which said switching elements are photoconductors, said switch operators are electroluminescent lamps, and said means operable in response to an output signal is an electroluminescent lamp switch operator, arranged to luminesce under an output signal, and the means to inhibit alternate-output signals is a photoconductor arranged 'to'connect vgroundrpotential to said alternate-output ter- 6. A universal logic block as described in claim 2, in which said switch elements are superconductors, and said switch operators are superconductor field-producing elements.

References Cited in the le of this patent Mellon Institute of Industrial Research, Quarterly Report No. 3, Second Series of the Computer Components Fellowship No. 347, April 1, 1954 to June 370, 1954, August 2, 1954. Y

Proceedings of the I.R.E. December, 1955; pages `1897 to 1906. v

Journal British I.R.E., March, 1957; pages 141 to 154. 

